我有以下代码:
module s(clock, direction, readWrite, LA1, LA2, LA3, LA4, LD1, LD2, LD3, LD4, RA1, RA2, RA3, RA4, RD1, RD2, RD3, RD4);
// parameters
input clock, direction, readWrite;
inout reg [7:0] LD1, LD2, LD3, LD4, RD1, RD2, RD3, RD4;
inout reg [11:0] LA1, LA2, LA3, LA4, RA1, RA2, RA3, RA4;
// code
always @(posedge clock) begin
if(direction==1) begin // left to right
assign RA1 = LA1 | LA2 | LA3 | LA4;
assign RD1 = LD1 | LD2 | LD3 | LD4;
assign { RA2, RA3, RA4 } = RA1;
assign { RD2, RD3, RD4 } = RD1;
end else begin
if(direction==1) begin // right to left
assign LA1 = RA1 | RA2 | RA3 | RA4;
assign LD1 = RD1 | RD2 | RD3 | RD4;
assign { LA2, LA3, LA4 } = LA1;
assign { LD2, LD3, LD4 } = LD1;
end
end
end
endmodule
但是,在第二行中,“inout reg [7:0] LD1,…”声明在VeritakWin 3.84F中引发语法错误。(因为Veritak允许“output reg”,因此在给定代码之后,我的程序中有类似的代码)。如果我删除“reg”,我会在分配行中出现错误。如果我删除“inout”,显然会出现错误。我甚至尝试删除“assign”关键字,或者用“<=”替换“=”,但仍然存在错误。我做错了什么?(我是Verilog的新手)
inout
端口不能声明为reg
,因为它们既可以用作输入端口(作为线),也可以用作输出端口(作为reg
或线)。 - sharvil111