VHDL - 如何在测试台中创建时钟？

Question

我应该如何在测试平台上创建一个时钟？我已经找到了一个答案，然而其他人在stackoverflow上建议有替代或更好的方法来实现这一点：

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test_tb IS 
END test_tb;

ARCHITECTURE behavior OF test_tb IS

    COMPONENT test
        PORT(clk : IN std_logic;)
    END COMPONENT;

   signal clk : std_logic := '0';
   constant clk_period : time := 1 ns;

BEGIN

   uut: test PORT MAP (clk => clk);       

   -- Clock process definitions( clock with 50% duty cycle is generated here.
   clk_process :process
   begin
        clk <= '0';
        wait for clk_period/2;  --for 0.5 ns signal is '0'.
        clk <= '1';
        wait for clk_period/2;  --for next 0.5 ns signal is '1'.
   end process;

END;

（来自这里）

- alexdavey

---

这个方法完全没问题。 - Qiu

Answer 1

我喜欢的技术：

signal clk : std_logic := '0'; -- make sure you initialise!
...
clk <= not clk after half_period;

我通常会扩展这个功能，加入一个 finished 信号来允许我停止计时：

我通常使用 finished 信号来停止计时：

clk <= not clk after half_period when finished /= '1' else '0';

如果您在测试环境中使用std_logic类型的信号finished，它可以由所有项目驱动:

signal finished : std_logic;

....
stimulus_process:process
begin
   finished <= '0';
   drive_various_signals_sync_with_clk;
   finished <= '1';
end process;

monitor_process:process
begin
   finished <= '0';
   check_all_signals_until_all_tests_complete;
   finished <= '1';
end process;

然后，当所有元素完成后，时钟才会停止。当没有更多的交易（信号）计划时，您的仿真将干净地停止。

---

小心警告： 如果您通过除以2从另一个常量计算half_period，则需要注意。 仿真器有一个“时间分辨率”设置，通常默认为纳秒...在这种情况下，5 ns / 2将变成2 ns，因此您最终得到的周期为4ns！将仿真器设置为皮秒，一切都会好起来的（直到您需要用皮秒的一部分来表示时钟时间为止！）

- Martin Thompson

---

先生，您如何定义信号完成？我不明白时钟如何在完成时停止？ - Yaakov

Answer 2

如果使用不同频率生成多个时钟，则可以通过调用并发过程来简化时钟生成。马丁·汤普森提到的时间分辨率问题可以通过在过程中使用不同的高低时间来部分缓解。时钟生成测试台和过程如下：

如果使用不同频率生成多个时钟，则可以通过调用并发过程来简化时钟生成。马丁·汤普森提到的时间分辨率问题可以通过在过程中使用不同的高低时间来部分缓解。时钟生成测试台和过程如下：

library ieee;
use ieee.std_logic_1164.all;

entity tb is
end entity;

architecture sim of tb is

  -- Procedure for clock generation
  procedure clk_gen(signal clk : out std_logic; constant FREQ : real) is
    constant PERIOD    : time := 1 sec / FREQ;        -- Full period
    constant HIGH_TIME : time := PERIOD / 2;          -- High time
    constant LOW_TIME  : time := PERIOD - HIGH_TIME;  -- Low time; always >= HIGH_TIME
  begin
    -- Check the arguments
    assert (HIGH_TIME /= 0 fs) report "clk_plain: High time is zero; time resolution to large for frequency" severity FAILURE;
    -- Generate a clock cycle
    loop
      clk <= '1';
      wait for HIGH_TIME;
      clk <= '0';
      wait for LOW_TIME;
    end loop;
  end procedure;

  -- Clock frequency and signal
  signal clk_166 : std_logic;
  signal clk_125 : std_logic;

begin

  -- Clock generation with concurrent procedure call
  clk_gen(clk_166, 166.667E6);  -- 166.667 MHz clock
  clk_gen(clk_125, 125.000E6);  -- 125.000 MHz clock

  -- Time resolution show
  assert FALSE report "Time resolution: " & time'image(time'succ(0 fs)) severity NOTE;

end architecture;

时间分辨率以信息形式在终端上打印，使用测试台中最后的并发断言。

如果clk_gen过程放置在单独的包中，则从一个测试台到另一个测试台的重复使用变得直接简单。

时钟波形如下图所示。

过程中还可以创建更高级的时钟生成器，它可以随着时间调整周期以匹配所请求的频率，尽管受时间分辨率限制。这在此处显示：

-- Advanced procedure for clock generation, with period adjust to match frequency over time, and run control by signal
procedure clk_gen(signal clk : out std_logic; constant FREQ : real; PHASE : time := 0 fs; signal run : std_logic) is
  constant HIGH_TIME   : time := 0.5 sec / FREQ;  -- High time as fixed value
  variable low_time_v  : time;                    -- Low time calculated per cycle; always >= HIGH_TIME
  variable cycles_v    : real := 0.0;             -- Number of cycles
  variable freq_time_v : time := 0 fs;            -- Time used for generation of cycles
begin
  -- Check the arguments
  assert (HIGH_TIME /= 0 fs) report "clk_gen: High time is zero; time resolution to large for frequency" severity FAILURE;
  -- Initial phase shift
  clk <= '0';
  wait for PHASE;
  -- Generate cycles
  loop
    -- Only high pulse if run is '1' or 'H'
    if (run = '1') or (run = 'H') then
      clk <= run;
    end if;
    wait for HIGH_TIME;
    -- Low part of cycle
    clk <= '0';
    low_time_v := 1 sec * ((cycles_v + 1.0) / FREQ) - freq_time_v - HIGH_TIME;  -- + 1.0 for cycle after current
    wait for low_time_v;
    -- Cycle counter and time passed update
    cycles_v := cycles_v + 1.0;
    freq_time_v := freq_time_v + HIGH_TIME + low_time_v;
  end loop;
end procedure;

再次通过软件包复用将是不错的选择。

- Morten Zilmer

Answer 3

并发信号赋值：

library ieee;
use ieee.std_logic_1164.all;

entity foo is
end;
architecture behave of foo is
    signal clk: std_logic := '0';
begin
CLOCK:
clk <=  '1' after 0.5 ns when clk = '0' else
        '0' after 0.5 ns when clk = '1';
end;

ghdl -a foo.vhdl ghdl -r foo --stop-time=10ns --wave=foo.ghw ghdl:info: 模拟由于 --stop-time 设置而停止 gtkwave foo.ghw

模拟器可以模拟进程，并将其转换为与您的进程语句等效的进程。模拟时间意味着在驱动事件进行敏感性子句或敏感性列表时使用wait for或after。

- user1155120

Answer 4

如何使用时钟和执行断言

本例演示了如何生成时钟，并为每个周期提供输入和断言输出。这里测试了一个简单的计数器。

关键思想是process块并行运行，因此时钟与输入和断言并行生成。

library ieee;
use ieee.std_logic_1164.all;

entity counter_tb is
end counter_tb;

architecture behav of counter_tb is
    constant width : natural := 2;
    constant clk_period : time := 1 ns;

    signal clk : std_logic := '0';
    signal data : std_logic_vector(width-1 downto 0);
    signal count : std_logic_vector(width-1 downto 0);

    type io_t is record
        load : std_logic;
        data : std_logic_vector(width-1 downto 0);
        count : std_logic_vector(width-1 downto 0);
    end record;
    type ios_t is array (natural range <>) of io_t;
    constant ios : ios_t := (
        ('1', "00", "00"),
        ('0', "UU", "01"),
        ('0', "UU", "10"),
        ('0', "UU", "11"),

        ('1', "10", "10"),
        ('0', "UU", "11"),
        ('0', "UU", "00"),
        ('0', "UU", "01")
    );
begin
    counter_0: entity work.counter port map (clk, load, data, count);

    process
    begin
        for i in ios'range loop
            load <= ios(i).load;
            data <= ios(i).data;
            wait until falling_edge(clk);
            assert count = ios(i).count;
        end loop;
        wait;
    end process;

    process
    begin
        for i in 1 to 2 * ios'length loop
            wait for clk_period / 2;
            clk <= not clk;
        end loop;
        wait;
    end process;
end behav;

计数器将如下所示：

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all; -- unsigned

entity counter is
    generic (
        width : in natural := 2
    );
    port (
        clk, load : in std_logic;
        data : in std_logic_vector(width-1 downto 0);
        count : out std_logic_vector(width-1 downto 0)
    );
end entity counter;

architecture rtl of counter is
    signal cnt : unsigned(width-1 downto 0);
begin
    process(clk) is
    begin
        if rising_edge(clk) then
            if load = '1' then
                cnt <= unsigned(data);
            else
                cnt <= cnt + 1;
            end if;
        end if;
    end process;
    count <= std_logic_vector(cnt);
end architecture rtl;

相关链接: https://electronics.stackexchange.com/questions/148320/proper-clock-generation-for-vhdl-testbenches

- Ciro Santilli OurBigBook.com