In verilog, I can assign a string to a vector like:
wire [39:0] hello; assign hello = "hello";
In VHDL, I'm having difficulty finding a method like this:
SIGNAL hello : OUT std_logic_vector (39 DOWNTO 0); ... hello <= "hello";
我一直在使用:
hello <= X"65_68_6c_6c_6f";
"
对于大字符串而言,这是不清晰且耗时的。
我查看了textio
包和txt_util
包,但两者都没有很清楚地说明如何解释字符串并将其转换为std_logic。
在VHDL中,是否有一种简单的方法将ASCII代码分配给std_logic?
以下是一个最小示例:
"LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY test IS
PORT(
ctrl : IN std_logic;
stdout : OUT std_logic_vector (39 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE rtl OF test IS
SIGNAL temp : std_logic_vector (39 DOWNTO 0);
BEGIN
stdout <= temp;
PROCESS(ctrl)
BEGIN
IF (ctrl = '0') THEN
temp <= "hello"; -- X"68_65_6C_6C_6F";
ELSE
temp <= "world";
END IF;
END PROCESS;
END rtl;